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HDD128M72D18RPW
DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register Part No. HDD128M72D18RPW
GENERAL DESCRIPTION
The HDD128M72D18RPW is a 128M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module. The module consists of eighteen CMOS 64M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD128M72D18RPW is a DIMM( Dual in line Memory Module) .Synchronous design allows precise cycle c ontrol with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance mem ory system applications. All module components may be powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
* Part Identification HDD128M72D18RPW - 13A HDD128M72D18RPW - 13B HDD128M72D18RPW - 16B : : : 133MHz (CL=2) 133MHz (CL=2.5) 166MHz (CL=2.5)
* 1024MB(64Mx72) Registered DDR DIMM based on 64Mx8 DDR SDRAM * 2.5V 0.2V VDD and VDDQ power supply * Auto & self refresh capability (8K Cycles / 64ms) * All input and output are compatible with SSTL_2 interface * Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock * All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock * MRS cycle with address key programs - Latency (Access from column address) : 2, 2.5 - Burst length : 2, 4, 8 - Data scramble : Sequential & Interleave * Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock * All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock * The used device is 16M x 8bit x 4Banks DDR SDRAM
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PIN ASSIGNMENT
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
HDD128M72D18RPW
Front
VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ * CK1 * /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 53 54 55 56 57 58 59 60 61
PIN
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Back
A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40
PIN
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
Frontl
VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD * /CS2 DQ48 DQ49 VSS * CK2 * /CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL
PIN
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
Back
VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC *A13 VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ * BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23
PIN
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Front
VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8 A10 CB6 VDDQ CB7 KEY
PIN
154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
Back
/RAS DQ45 VDDQ /CS0 /CS1 DM5 VSS DQ46 DQ47 * /CS3 VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
145 146 147 148 149 150 151 152 153
VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44
* : These pins are not used in this module. PIN A0~A12 BA0~BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS8 DM0~DM8 CK0~/CK0 CKE0~CKE1 /CS0~/CS1 /RAS /CAS PIN DESCRIPTION Address input Bank Select Address Data input/output Check Bit Data Strobe input/output Data-in Mask Clock input Clock enable input Chip Select input Row Address strobe Column Address strobe PIN VDD VDDQ VREF VDDSPD VSS SA0~SA2 SDA SCL VDDID NC PIN DESCRIPTION Power supply(2.5V) Power supply for DQs(2.5V) Power supply for reference Serial EEPROM Power supply(3.3) Ground Address in EEPROM Serial data I/O Serial clock VDD identification flag No connection
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HANBit Functional Block Diagram
HDD128M72D18RPW
A0-A12
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PIN FUNCTION DESCRIPTION
Pin CK, /CK Name Clock Input Function
HDD128M72D18RPW
CK and /CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of /CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/ /CK. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in CKE Clock Enable any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognizean LVCMOS LOW level prior to VREF being stable on power-up. CS enables(registered LOW) and disables(registered HIGH) the command decoder. /CS0, /CS1 Chip Select All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. A0 ~ A12 BA0 ~ BA1 /RAS /CAS /WE DQS0 ~ 7 Address Bank select address Row address strobe Column address strobe Write enable Data Strobe Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11 BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE command is being applied. Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. Output with read data, input with write data. Edge-aligned with read data, cen-tered in write data. Used to capture write data. DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH DM0~7 Input Data Mask along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing. DQ0 ~ 63 VDDQ VDD VSS VREF VSPD VDDID Data input/output Supply Supply Supply Supply Supply Data inputs/outputs are multiplexed on the same pins. DQ Power Supply : +2.5V 0.2V. Power Supply : +2.5V 0.2V (device specific). DQ Ground. SSTL_2 reference voltage. Serial EEPROM Power Supply : 3.3v VDD identification Flag
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Absolute Maximum Ratings
PARAMETER Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Storage temperature Power dissipation Short circuit current SYMBOL VIN, VOUT VDD VDDQ TSTG PD IOS
HDD128M72D18RPW
RATING -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 1.5 * # of component 50 UNTE V V V C W mA
Notes: Operation at above absolute maximum rating can adversely affect device reliability
DC operating conditions
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70C) ) PARAMETER Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage(system) Input High Voltage Input Low Voltage Input Voltage Level, CK and /CK inputs Input Differential Voltage, CK and /CK inputs Input leakage current Output leakage current Output High current (Normal strength driver) ; VOUT=VTT + 0.84V Output Low current (Normal strength driver) ; VOUT=VTT - 0.84V Output High current (Half strength driver) ; VOUT=VTT + 0.45V Notes : 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled to VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 3nH. 2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and SYMBOL VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) I LI I OZ I OH I OL I OH MIN 2.3 2.3 0.49*VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.3 -2 -5 -16.8 16.8 -9 MAX 2.7 2.7 0.51*VDDQ VREF + 0.04 VREF + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 2 5 UNIT V V V V V V V V uA uA mA mA mA 3 1 2 NOTE
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Input / Output Capacitance
(VDD = min to max, VDDQ = 2.5V to 2.7V, TA = 25C, f = 100MHz) DESCRIPTION Input capacitance(A0~A12, BA0~BA1, /RAS, /CAS,/WE) Input capacitance(CKE0,CKE1) Input capacitance(/CS0) Input capacitance(CK0~CK2, /CK0~/CK2) Input capacitance(DM0~DM7) Data input/output capacitance (DQ0 ~ DQ63, DQS0~DQS7) Data input/output capacitance (CB0~CB7) SYMBOL CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 COUT2 MIN 9 9 9 11 14 14 14
HDD128M72D18RPW
MAX 11 11 11 12 16 16 16
UNITS pF pF pF pF pF pF pF
DC Characteristics
(VDD = 2.7V, T =10C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 Normal IDD6 IDD7A Low Power -16B (DDR333@CL=2.5) 2230 2500 590 1420 950 1040 1690 2540 2630 3130 590 560 4520 -13A (DDR266@CL=2.0) 2010 2280 540 1290 900 990 1560 2280 2330 2910 540 510 4080 -13B (DDR266@CL=2.5) 2010 2280 540 1290 900 990 1560 2280 2330 2910 540 510 4080 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
Notes: Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. AC Operating Conditions PARAMETER Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. STMBOL VIH (AC) VIL (AC) VID (AC) VIX (AC) 0.7 0.5*VDDQ-0.2 MIN VREF + 0.35 VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 V V V 1 2 MAX UNIT NOTE
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HDD128M72D18RPW
AC characteristics
(THESE AC CHARACTERISTICS WERE TESTED ON THE COMPONENT) DDR333@CL=2.5 PARAMETER SYMBOL MIN Row cycle time Refresh row cycle time Row active time /RAS to /CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2.0 Clock cycle time CL=2.5 Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS-in falling edge to CK rising-setup time DQS-in falling edge to CK rising hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time(Fast) Address and Control Input hold time(Fast) Address and Control Input setup time(Slow) URL : www.hbe.co.kr REV 1.0 (January. 2005) tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tCK 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 7 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.1 12 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 1.25 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.1 12 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 1.25 ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns i,5.7~9 i,5.7~9 i, 6~9 3 12 tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD 60 72 42 18 18 12 15 1 1 7.5 12 70K -16B MAX MIN 65 75 45 20 20 15 15 1 1 7.5 12 120K DDR266A@CL=2.0 -13A MAX MIN 65 75 45 20 20 15 15 1 1 10 12 120K DDR266B@CL=2.5 -13B MAX ns ns ns ns ns ns tCK tCK tCK ns UNIT NOTE
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Address and Control Input hold time(Slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Input Slew Rate(for input only pins) Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) Output Slew Rate(x16) Output Slew Rate Matching Ratio(rise to fall) Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time tIH tHZ t LZ t SL(IO) t SL(O) t SL(O) t SL(O) t SLMR tMRD tDS tDH
tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH tHP
HDD128M72D18RPW
0.8 -0.7 -0.7 0.5 0.5 1.0 0.7 0.67 12 0.45 0.45
2.2 1.75 6 75 200 7.8 tHP -tQHS tCLmin or tCHmin tQHS tWPST tRAP (tWR/tCK)+ (tRP/tCK) 0.4
1.0 +0.7 +0.7 -0.75 -0.75 0.5 0.5 4.5 5 1.5 1.0 0.7 0.67 15 0.5 0.5
2.2 1.75 7.5 75 200 7.8 tHP -tQHS tCLmin or tCHmin
1.0 +0.75 +0.75 -0.75 -0.75 0.5 0.5 4.5 5 1.5 1.0 0.7 0.67 15 0.5 0.5
2.2 1.75 7.5 75 200 7.8 tHP -tQHS tCLmin or tCHmin
ns +0.75 +0.75 ns ns ns tCK 4.5 5 1.5 ns ns ns ns ns ns ns tCK ns 0.75
i, 6~9 1 1
tCK
j, k j, k 8 8
4 11 10,11 11
2
0.55 0.6 18
0.75
ns ns ns tCK
0.4
0.6 20
0.4
0.6 20
tDAL
(tWR/tCK)+ (tRP/tCK)
(tWR/tCK)+ (tRP/tCK)
tCK
13
Notes : Maximum burst refresh of 8. tHZQ transitions occurs in the same assess time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving. The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly.
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System Characteristics for DDR SDRAM
HDD128M72D18RPW
The following specification parameters are required in systems using DDR333, DDR266 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) SYMBOL DCSLEW DDR333 MIN TBD MAX TBD DDR266 MIN TBD MAX TBD Units V/ns Notes a, m
Table 2 : Input Setup & Hold Time Derating for Slew Rate
INPUT SLEW RATE 0.5 V/ns 0.4 V/ns 0.3 V/ns TIS 0 +50 +100 TIH 0 0 0 UNITS ps ps ps NOTES i i i
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
INPUT SLEW RATE 0.5 V/ns 0.4 V/ns 0.3 V/ns TDS 0 +75 +150 TDH 0 +75 +150 UNITS ps ps ps NOTES k k k
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
DELTA SLEW RATE +/- 0.0 V/ns +/- 0.25 V/ns +/- 0.5 V/ns TDS 0 +50 +100 TDH 0 +50 +100 UNITS ps ps ps NOTES j j j
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
SLEW RATE CHARACTERISTIC Pullup Slew Rate Pulldown slew TYPICAL RANGE (V/NS) 1.2 ~ 2.5 1.2 ~ 2.5 MINIMUM (V/NS) 1.0 1.0 MAXIMUM (V/NS) 4.5 4.5 NOTES a,c,d,f,g,h b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
SLEW RATE CHARACTERISTIC Pullup Slew Rate Pulldown slew TYPICAL RANGE (V/NS) 1.2 ~ 2.5 1.2 ~ 2.5 MINIMUM (V/NS) 0.7 0.7 MAXIMUM (V/NS) 5.0 5.0 NOTES a,c,d,f,g,h b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS PARAMETER Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR333 MIN TBD MAX TBD DDR266 MIN TBD MAX TBD Notes e,m
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Component Notes
HDD128M72D18RPW
1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ). 2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 5. For command/address input slew rate 6. For command/address input slew rate 7. For CK & CK slew rate 1.0 V/ns 1.0 V/ns 0.5 V/ns and < 1.0 V/ns
8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 9. Slew Rate is measured between VOH(ac) and VOL(ac). 10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 11. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and pchannel to n-channel variation of the output drivers. 12. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 13. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks
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System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
HDD128M72D18RPW
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 C (T Ambient), VDDQ = 2.5V, typical process Minimum : 70 C (T Ambient), VDDQ = 2.3V, slow - slow process Maximum : 0 C (T Ambient), VDDQ = 2.7V, fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotony.
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SIMPLIFIED TRUTH TABLE
COMMAND Register Register Extended MRS Mode register set Auto refresh Refresh Self refresh Entry Exit CKE n-1 H H H L H H CKE n X X H L H X X /R /CS L L L L H L L A S L L L H X L H /C A S L L L H X H L L L H H X H H H H H H H L H X X X L H L L L L H L X H L H L H L H H L X V X X H X V X X X H X H X H L H H X V X X H X V L L L X V X X H X V X X X X X X X X X X X X /WE DM
HDD128M72D18RPW
BA 0,1
A10/ AP OP code OP code X X
A11,A12 A9~A0
NOTE 1,2 1,2 3 3 3 3 4 4 4 4,6 7
Bank active & row addr. Read & column address Write & column address Auto precharge disable Auto precharge eable Auto precharge disable Auto precharge enable Burst Stop Precharge Bank selection All banks Entry Exit Entry
V L V H L V H
Row address Column Address Column Address X
V X
L H X
X
5
Clock suspend or active power down
Precharge power down mode
X X V X X X 8
Exit DM
L H H
H
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0) URL : www.hbe.co.kr REV 1.0 (January. 2005) 12 HANBit Electronics Co.,Ltd.
HANBit
PACKAGING INFORMATION
Unit : mm
HDD128M72D18RPW

133.35 0.20
30.48 0.20
A
B
< Rear - Side >
133.35 0.20
30.48 0.20
***
PCB Thickness : 1.27 0.08 mm
URL : www.hbe.co.kr REV 1.0 (January. 2005)
13
HANBit Electronics Co.,Ltd.
HANBit
ORDERING INFORMATION
Part Number Density Org. Package 184PIN DIMM 184PIN DIMM 184PIN DIMM Ref.
HDD128M72D18RPW
Vcc
MODE DDR Registered DDR Registered DDR Registered
MAX.frq 166MHz/CL2 DDR333 133MHz/CL2 DDR266 133MHz/CL2.5 DDR266
HDD128M72D18RPW-16B
1024MByte
128M x 72
8K
2.5V
HDD128M72D18RPW-13A
1024MByte
128M x 72
8K
2.5V
HDD128M72D18RPW-13B
1024MByte
128M x 72
8K
2.5V
URL : www.hbe.co.kr REV 1.0 (January. 2005)
14
HANBit Electronics Co.,Ltd.

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